Layout Optimization in VLSI Design Breitscheidstr. 10 Hans-Georg Räder) 2

Hans-Georg Räder) 2

bis zur Mitte des XVI

Band: Julius Verne's Schriften IX

welchen in dem Bericht ¿Dreaming to the Path 2050¿ von der Investment Bank Goldman Sachs eine glorreiche Zukunft bescheinigt wird

This research work has also been published as a special issue of the journal Formal Methods in System Design

Layout Optimization in VLSI Design Breitscheidstr. 10 Hans-Georg Räder) 2Introduction The exponential scaling of feature sizes in semiconductor technologies has side effects on layout optimization, related to effects such as inter connect delay, noise and crosstalk, signal integrity, parasitics effects, and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary, and advanced layout opti mization